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MYSON TECHNOLOGY
FEATURES
* IEEE802.3 and IEEE802.3u compliant. * Single chip, low cost, two port switch controller. * Build_in embedded memory on chip for packet buffering. * Provide 2 MII/RMII (Reduced Media Independent Interface) ports. * A flexible MII interface design can directly connect with standard MII or pseudo MII. * Support half/full duplex operation per port. * Optional back_pressure control for half_duplex mode. * Provide "store and forward" switching, and forwarding rate at full_wire speed. * Support up to 2048 MAC addresses filtering database, and automatical address aging_out function (300 secs). * Low power CMOS design, with single 3.3V supply voltage, 50 MHZ operation. * Provide 128 pin PQFP package (MTD502EF), and 80 pin LQFP package (MTD502EG).
MTD502E
2 Port 10M/100M Switch With Build_in Memory
GENERAL DESCRIPTION
The MTD502E is a highly integrated, 10M/ 100M two port switch controller with build_in embedded memory. It supports 2 MII/RMII ports for 10M/100M operation, and both can operate under half or full duplex mode. The MTD502E is an ideal solution for two port bridge or dual speed hub application, and no need any external memory buffers in application design. The flexible MII interface design can directly connect with pseudo MII interface (Am79c901, HomePNA PHY). The MTD502E provides packet forwarding, address filtering, learning, and aging function, and have an optional back_presure control implemented in half duplex mode. The MTD502E supports an effective address filtering database, which can recognize up to 2048 MAC addresses. It also support an automatical aging function for address table updating (aging time is 300 secs default).
BLOCK DIAGRAM
Port0 DMA
Two Port Switch Engine
MAC0
MII0
Embedded Memory
Port1 DMA
MAC1
MII1
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 1/20 MTD502E Revision 1.3 12/07/2000
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SYSTEM DIAGRAM
1). Two Port Switch Application (HomePNA to LAN)
MTD502E
MTD502E
MII1 MII0
HomePNA PHYsceiver
10M/100M PHYsceiver
Transformer
Transformer
RJ11
RJ45
2). Dual Speed Hub Application
MTD502E
10M/100M Repeater (Without 2P_sw)
10M/100M Repeater (Without 2P_sw)
.......
Expansion Bus
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product.E 2/20 MTD502E Revision 1.3 12/07/2000
1.0 PIN CONNECTION (under MII mode)
1) 128 Pin PQFP (MTD502EF)
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VCC NC GND NC NC NC NC NC NC NC NC CLK25OUT NC NC GND NC NC NC VCC SYSCLK GND NC NC NC NC RSTB 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
MTD502EF
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LINK0 TXD0_3 VCC TXD0_2 NC NC NC NC TXD0_1 TXD0_0 TXEN0 TXC0 NC GND RXC0 NC NC NC RXD0_0 RXD0_1 FULL0 NC NC NC RXD0_2 RXD0_3 RXDV0 CRS0 COL0 SPEED0 VCC GND LINK1 TXD1_3 TXD1_2 NC NC NC 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 NC NC NC NC LNKRX0_LED LNKRX1_LED LNKACT0_LED LNKACT1_LED FDCOL0_LED FDCOL1_LED GND COL0_LED COL1_LED NC NC NC NC NC NC NC GND NC NC NC NC NC NC NC GND NC VCC NC NC NC NC VCC NC NC
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
MTD502E
SPEED1 COL1 CRS1 RXDV1 GND VCC RXD1_3 RXD1_2 NC NC NC FULL1 RXD1_1 RXD1_0 NC NC NC RXC1 GND VCC NC TXC1 TXEN1 TXD1_0 TXD1_1 NC
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2) 80 Pin LQFP (MTD502EG)
NC NC LNKRX0_LED LNKRX1_LED LNKACT0_LED LNKACT1_LED FDCOL0_LED FDCOL1_LED GND GND COL0_LED COL1_LED GND GND GND GND VCC VCC SPEED1 VCC
MTD502E
NC VCC NC GND NC NC NC NC NC NC NC CLK25OUT VCC SYSCLK NC RSTB LINK0 TXD0_3 VCC TXD0_2
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
MTD502EG
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
COL1 CRS1 RXDV1 GND VCC RXD1_3 RXD1_2 NC FULL1 RXD1_1 RXD1_0 RXC1 TXC1 TXEN1 TXD1_0 TXD1_1 NC TXD1_2 TXD1_3 LINK1
NC TXD0_1 TXD0_0 TXEN0 TXC0 GND RXC0 NC NC NC RXD0_0 RXD0_1 FULL0 NC RXD0_2 RXD0_3 RXDV0 CRS0 COL0 SPEED0
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20
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2.0 PIN DESCRIPTIONS
MTD502E
MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations Pin No. 1 2 3 4 5 6~8 9 10 11 12 13 14 15 16 17 18 19 20 21 22~24 25 26 27 28 29 30 31 32 33 34 35 36 37,38 39 40 41 42 43 44 45 I/O I O VCC O O I O O O I I GND I O O O I I I O I I I I I I VCC GND I O O O I I O O O I I VCC MII mode LINK0 Phy_MII mode (NC) Rmii mode LINK0 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) CRSDV0 TXD0_1 TXD0_0 TXEN0 RXD0_0 RXD0_1 FULL0 (NC) (NC) (NC) (NC) SPEED0 (NC) (NC) Phy_Rm Descriptions ii mode (NC) Pin 1~32 for Port0, suitable for connecting with 10/ 100PHY , RISC_CPU, Switch,.... (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) TXEN0 RXD0_1 RXD0_0 CRSDV0 TXD0_0 TXD0_1 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
TXD0_3 RXD0_3 TXD0_2 RXD0_2 (NC) CRS0 (NC) (NC) TXD0_1 RXD0_1 TXD0_0 RXD0_0 TXEN0 RXDV0 TXC0 (NC) (NC) (NC) RXC0 (NC) (NC) (NC) RXD0_0 RXD0_1 FULL0 (NC) RXD0_2 RXD0_3 RXDV0 CRS0 COL0 SPEED0 (NC) RXC0 COL0 TXC0 TXD0_0 TXD0_1 FULL0 (NC) TXD0_2 TXD0_3 TXEN0 SPEED0 (NC) (NC)
LINK1 TXD1_3 TXD1_2 (NC) (NC) (NC) TXD1_1 TXD1_0 TXEN1 TXC1 (NC)
(NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
LINK1 (NC) (NC) (NC) (NC) CRSDV1 TXD1_1 TXD1_0 TXEN1 RXD1_0 RXD1_1
(NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
Pin 33~64 for Port1, suitable for connecting with HomePNA PHY.
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Pin No. 46 47 48~50 51 52 53 54~56 57 58 59 60 61 62 63 64 65~66 67 68~71 72 73 74 75,76 77~79 80 81 82 83~85 86~88 89 90 I/O GND I O I I I O I I VCC GND I I I I I VCC IO VCC IO GND IO I O IO GND IO I O IO MII mode RXC1 (NC) RXD1_0 RXD1_1 FULL1 (NC) RXD1_2 RXD1_3 Phy_MII mode (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) Rmii mode FULL1 (NC) (NC) (NC) SPEED1 (NC) (NC) (NC) Phy_Rm ii mode (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
MTD502E
MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations Descriptions
RXDV1 CRS1 COL1 SPEED1 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) Co1_D
(NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) Co1_D
(NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) Co1_D
(NC) (NC) (NC) (NC) (NC) * (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) Co1_D Port1: COL LED display, low_active. * when in half duplex mode: this LED pin present port1' collision event. s Co0_D Port0: COL LED display, low_active. * when in half duplex mode: this LED pin present port0' collision event. s
91
IO
Co0_D
Co0_D
Co0_D
92 93
GND IO FdCo1_D FdCo1_D FdCo1_D FdCo1_D Port1: FULL/COL LED display, low_active. * when in full duplex mode: this LED pin is always in low_active. when in half duplex mode: this LED pin present port1' collision event, using flash style for display. s
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Pin No. 94 I/O IO
MTD502E
MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Rmii Phy_Rm Descriptions mode mode mode ii mode FdCo0_D FdCo0_D FdCo0_D FdCo0_D Port0: FULL/COL LED display, low_active. * when in full duplex mode: this LED pin is always in low_active. when in half duplex mode: this LED pin present port0' collision event, using flash style for display. s LnAc1_D LnAc1_D LnAc1_D LnAc1_D Port1: Link_Activity LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Tx or Rx activity in this port : this LED pin present port1' Tx/Rx activity, using flash style s for display. LnAc0_D LnAc0_D LnAc0_D LnAc0_D Port0: Link_Activity LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Tx or Rx activity in this port : this LED pin present port0' Tx/Rx activity, using flash style s for display. LnRx1_D LnRx1_D LnRx1_D LnRx1_D Port1: Link_Rx LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Rx activity in this port : this LED pin present port1' Rx activity, using flash style for diss play. LnRx0_D LnRx0_D LnRx0_D LnRx0_D Port0: Link_Rx LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Rx activity in this port : this LED pin present port0' Rx activity, using flash style for diss play. 99~102 103 104 105 106~110 111 112 113 114 115~116 117 118~120 121 122 123 IO (NC) (NC) (NC) (NC) VCC IO (NC) (NC) (NC) (NC) GND IO (NC) (NC) (NC) (NC) IO (NC) P0MDIO (NC) P0MDIO IO (NC) P0MDC (NC) P0MDC IO (NC) (NC) (NC) (NC) IO CLK25O CLK25O CLK25O CLK25O clock 25Mhz output. IO (NC) (NC) (NC) (NC) GND IO (NC) (NC) (NC) (NC) VCC I SYSCLK SYSCLK SYSCLK SYSCLK system clock input, 50Mhz operation. GND
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95
IO
96
IO
97
IO
98
IO
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Pin No. 124~127 128 I/O IO I MII mode (NC) RSTB Phy_MII mode (NC) RSTB Rmii mode (NC) RSTB
MTD502E
MTD502EF (128PQFP) Pin Definition Mapping Under Different Configurations Phy_Rm Descriptions ii mode (NC) RSTB system resetb input, low_active.
note: input signal LINK,SPEED,FULL from PHY device are low_active definnition.
MTD502EF(128PQFP) Jumper Setting Table After Power On Reset Pin No. 5 IO IO Setting Function 2P_Sw Enable Descriptions Jumper setting function after power on reset. -external pull_high = 1, means enter 2 port switch mode. -external pull_low = 0, means an internal test mode. -external floating : default is 0. For MTD502E application, this pin must always use "external pull_hgih" for well operation. Back Pressure Disable Jumper setting function after power on reset. -external pull_high = 1, means back_pressure function ( under half_duplex) is disabled for two ports both. -external pull_low = 0, means back_pressure function enable. 95 IO P1_Rmii Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port 1 RMII interface enable.. -external pull_low = 0, means Port 1 is MII interface. 97 IO P0_Rmii Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port 0 RMII interface enable.. -external pull_low = 0, means Port 0 is MII interface. 98 IO -external floating : default is 0. P0_Phy_Mode Enable Jumper setting function after power on reset. -external pull_high = 1, means Port 0 interrface enter PHY mode. -external pull_low = 0, means Port 0 interface is using MAC mode. 100 IO P1_Bkoff_4 Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port 1 MAC backoff engine is using limit_4 modified method. -external pull_low = 0, means Port 1 MAC backoff engine is using specification defined method. -external floating : default is 0.
18
IO
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Pin No. 101 IO IO Setting Function P0_Bkoff_4 Enable Descriptions Jumper setting function after power on reset.
MTD502E
MTD502EF(128PQFP) Jumper Setting Table After Power On Reset
-external pull_high = 1, means Port 0 MAC backoff engine is using limit_4 modified method. -external pull_low = 0, means Port 0 MAC backoff engine is using specification defined method. 102 IO DeviceID[4] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 104 IO DeviceID[3] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 106 IO DeviceID[2] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 107 IO DeviceID[1] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 108 IO DeviceID[0] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 109 IO P1_CRCchk Disable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port1 CRC check and drop function is disabled. -external pull_low = 0, means Port1 CRC check and drop function is enabled. -external floating : default is 0.
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Pin No. 110 IO IO Setting Function P0_CRCchk Disable Descriptions Jumper setting function after power on reset.
MTD502E
MTD502EF(128PQFP) Jumper Setting Table After Power On Reset
-external pull_high = 1, means Port0 CRC check and drop function is disabled. -external pull_low = 0, means Port0 CRC check and drop function is enabled. 126 IO VLAN tag Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means MAC receiving accept 1522 Bytes packet (VLAN tag enable). -external pull_low = 0, means MAC receiving reject 1522 Bytes packet (VLAN tag disable). -external floating : default is 0.
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3.0 MTD502EG (80LQFP) PIN DESCRIPTIONS
MTD502E
MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations Pin No. 1 I/O O MII mode (NC) Phy_MII mode CRS0 Rmii mode (NC) Phy_Rm Descriptions ii mode (NC) Pin 77~80, 1~20 for Port0, suitable for connecting with 10/100PHY , RISC_CPU, Switch,.... (NC) (NC) (NC) (NC) TXEN0 RXD0_1 RXD0_0 CRSDV0 TXD0_0 TXD0_1 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) Pin 21~41 for Port1, suitable for connecting with HomePNA PHY. (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
O O O I GND I O O O I I I O I I I I I I I O O O O O O I I I I I O I I VCC GND I I
TXD0_1 RXD0_1 TXD0_0 RXD0_0 TXEN0 RXDV0 TXC0 (NC) RXC0 (NC) (NC) (NC) RXD0_0 RXD0_1 FULL0 (NC) RXD0_2 RXD0_3 RXDV0 CRS0 COL0 SPEED0 LINK1 TXD1_3 TXD1_2 (NC) TXD1_1 TXD1_0 TXEN1 TXC1 RXC1 RXD1_0 RXD1_1 FULL1 (NC) RXD1_2 RXD1_3 (NC) RXC0 COL0 TXC0 TXD0_0 TXD0_1 FULL0 (NC) TXD0_2 TXD0_3 TXEN0 SPEED0 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
(NC) (NC) (NC) (NC) CRSDV0 TXD0_1 TXD0_0 TXEN0 RXD0_0 RXD0_1 FULL0 (NC) (NC) (NC) (NC) SPEED0 (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
RXDV1 CRS1
(NC) (NC)
(NC) (NC)
(NC) (NC)
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Pin No. 40 41 42 43 44 45 46 47 48 49 I/O MII mode COL1 Phy_MII mode (NC) (NC) Rmii mode (NC) (NC) Phy_Rm ii mode (NC) * (NC)
MTD502E
MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations Descriptions
I VCC I SPEED1 VCC VCC GND GND GND GND IO Co1_D
Co1_D
Co1_D
Co1_D Port1: COL LED display, low_active. * when in half duplex mode: this LED pin present port1' collision event. s Co0_D Port0: COL LED display, low_active. * when in half duplex mode: this LED pin present port0' collision event. s
50
IO
Co0_D
Co0_D
Co0_D
51 52 53
GND GND IO FdCo1_D FdCo1_D FdCo1_D FdCo1_D Port1: FULL/COL LED display, low_active. * when in full duplex mode: this LED pin is always in low_active. when in half duplex mode: this LED pin present port1' collision event, using s flash style for display. FdCo0_D FdCo0_D FdCo0_D FdCo0_D Port0: FULL/COL LED display, low_active. * when in full duplex mode: this LED pin is always in low_active. when in half duplex mode: this LED pin present port0' collision event, using s flash style for display. LnAc1_D LnAc1_D LnAc1_D LnAc1_D Port1: Link_Activity LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Tx or Rx activity in this port : this LED pin present port1' Tx/Rx s activity, using flash style for display.
54
IO
55
IO
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Pin No. 56 I/O IO
MTD502E
MTD502EG(80LQFP) Pin Definition Mapping Under Different Configurations MII Phy_MII Rmii Phy_Rm Descriptions mode mode mode ii mode LnAc0_D LnAc0_D LnAc0_D LnAc0_D Port0: Link_Activity LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Tx or Rx activity in this port : this LED pin present port0' Tx/Rx s activity, using flash style for display. LnRx1_D LnRx1_D LnRx1_D LnRx1_D Port1: Link_Rx LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Rx activity in this port : this LED pin present port1' Rx activity, s using flash style for display. LnRx0_D LnRx0_D LnRx0_D LnRx0_D Port0: Link_Rx LED display, low_active. * when in Link_On state : this LED pin is always in low_active. when have Rx activity in this port : this LED pin present port0' Rx activity, s using flash style for display. 59-61 62 63 64 65-69 70 71 72 73 74 75 76 77 78 79 80 IO VCC IO GND IO IO IO O VCC I IO I I O VCC O (NC) (NC) (NC) (NC) (NC) (NC) (NC) (NC)
57
IO
58
IO
(NC) (NC) (NC) (NC) (NC) P0MDIO (NC) P0MDIO (NC) P0MDC (NC) P0MDC CLK25O CLK25O CLK25O CLK25O clock 25Mhz output. SYSCLK SYSCLK SYSCLK SYSCLK system clock input, 50Mhz operation. (NC) (NC) (NC) (NC) RSTB RSTB RSTB RSTB system resetb input, low_active. LINK0 (NC) LINK0 (NC) TXD0_3 RXD0_3 (NC) (NC) TXD0_2 RXD0_2 (NC) (NC)
note: input signal LINK,SPEED,FULL from PHY device are low_active definnition.
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MTD502E
MTD502EG(80LQFP) Jumper Setting Table After Power On Reset Pin No. 1 IO IO Setting Function 2P_Sw Enable Descriptions Jumper setting function after power on reset. -external pull_high = 1, means enter 2 port switch mode. -external pull_low = 0, means an internal test mode. -external floating : default is 0. For MTD502E application, this pin must always use "external pull_hgih" for well operation. Back Pressure Disable Jumper setting function after power on reset. -external pull_high = 1, means back_pressure function ( under half_duplex) is disabled for two ports both. -external pull_low = 0, means back_pressure function enable. 57 IO P0_Rmii Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port 0 RMII interface enable.. -external pull_low = 0, means Port 0 is MII interface. 58 IO -external floating : default is 0. P0_Phy_Mode Enable Jumper setting function after power on reset. -external pull_high = 1, means Port 0 interrface enter PHY mode. -external pull_low = 0, means Port 0 interface is using MAC mode. 59 IO P1_Bkoff_4 Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port 1 MAC backoff engine is using limit_4 modified method. -external pull_low = 0, means Port 1 MAC backoff engine is using specification defined method. 60 IO P0_Bkoff_4 Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port 0 MAC backoff engine is using limit_4 modified method. -external pull_low = 0, means Port 0 MAC backoff engine is using specification defined method. 61 IO DeviceID[4] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. -external floating : default is 0.
10
IO
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Pin No. 63 IO IO Setting Function DeviceID[3] Descriptions Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 65 IO DeviceID[2] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 66 IO DeviceID[1] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 67 IO DeviceID[0] -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1. -external pull_low = 0. 68 IO P1_CRCchk Disable -external floating : default is 0. Jumper setting function after power on reset.
MTD502E
MTD502EG(80LQFP) Jumper Setting Table After Power On Reset
-external pull_high = 1, means Port1 CRC check and drop function is disabled. -external pull_low = 0, means Port1 CRC check and drop function is enabled. 69 IO P0_CRCchk Disable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means Port0 CRC check and drop function is disabled. -external pull_low = 0, means Port0 CRC check and drop function is enabled. 71 IO VLAN tag Enable -external floating : default is 0. Jumper setting function after power on reset. -external pull_high = 1, means MAC receiving accept 1522 Bytes packet (VLAN tag enable). -external pull_low = 0, means MAC receiving reject 1522 Bytes packet (VLAN tag disable). -external floating : default is 0.
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4.0 FUNCTIONAL DESCRIPTIONS
MTD502E
The MTD502E implements a 10/100M two port switch for 10M/100M packet switching. Total 2K address entrys are provided for packets'SA learning and DA routing; and also provide automatic aging function ( aging time = 300secs). When using in two port bridge application, the input packets from port0 will be stored in an embedded memory buffers of MTD502E first, while packets is good for forwarding ( CRC chech ok, 64Bytes < length > 1518Bytes, and not local packets ) , than forward this packet to port1.
4.1 Learning and Routing
The MTD502E supports 2K MAC entries for filtering. Dynamic address learning is performed by each good unicast packet is completely received. The routing process is performed whenever the packet' s DA is captured. If the DA get a hit result in self port' address table, this packet will be treated as a " s local packet", and then drop the packet forwarding to the other port. On the other hand, if this packet is not a "local packet", then will be forwarded to the other port.
4.2 Aging
The address entries are scheduled in the aging machine. If one station does not transmit any packet for a period of time, the belonging MAC address will be kicked out from the address table. The aging out time value is 300 seconds.
4.3 Buffer Queue Management
The buffer queue manager is implemented to manage the embedded memory packet buffering. The main function of the buffer queue manager is to maintain the linked list consists of buffer IDs, which is used to show the corresponding memory address for each incoming packet. In addition, the buffer queue manager monitors the rested free spaces status of the memory buffers, If the packet storage achieve the predefined threshold value, the buffer queue manager will raise the alarm signal which is used to enable the flow control mechanism for avoiding transmission ID queue overflow happening. MTD502E provide back pressure control scheme in half duplex mode.
4.4 Half Duplex Back Pressure Control
In half duplex mode, MTD502E provide a back pressure control mechanism to avoid dropping packets during network conjection situation. When the "back pressure control enable" bit is set during power on reset (pin_18 is external pull_low), it enables MTD502E supporting back pressure function in half_duplex mode; When output port buffer queue' on_using value reach the initialization setting s threshold value, MTD502E will send a JAM pattern in the input port when it senses an incoming packet , thus force a collision to inform the remote node transmission back off and will effectively avoid dropping packets. If the "back pressure control disable" bit is set, and there is no free buffer queue available for the incoming packets, the incoming packets will be dropped.
4.5 MAC and DMA engine
The MTD502E' MAC performs all the functions in IEEE802.3 protocol, such as frame formatting, s frame stripping, CRC checking, bad packet dropping, defering to line traffic, and collision handling. The MAC Rx_engine checks incoming packets and drops the bad packet which include CRC error, alignment error, short packet (less than 64 bytes), and long packet(more than 1518 bytes or 1522 bytes when the "VLAN tag 1522 bytes receive enable" bit is set during power on reset). Before transmission, The MAC Tx_engine will constantly monitor the line traffic using derfering precedure. Only if it has been idle for a 96 bits time (a minimum interpacket gap time, IPG time), actual transmmission can be started. For the half duplex mode, MAc engine will detect collision; if a collision is detected, the MAC Tx_engine will transmit a JAM pattern and then delay the re_transmission for a random time period determined by the back_off algorithm (MTD502E implements the truncated exponential back_off algorithm defined in IEEE 802.3 standard). For the full duplex mode, collision signal is ignored.
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MTD502E Revision 1.3 12/07/2000
MYSON TECHNOLOGY
5.0 Electrical Characteristics
5.1 Absolute Maximum Ratings
Symbol Parameter VCC Power Supply Voltage VIN VOUT TSTG Input Voltage Output Voltage Storage Temperature RATING -0.3 to 3.6 -0.3 to Vcc+0.3 -0.3 to Vcc+0.3 -55 to 150
MTD502E
Unit V V V
C
5.2 Recommended Operating Conditions
Symbol VCC Power Supply VIN Input Voltage Tj Parameter Min. 3.0 0 0 -40 Typ. 3.3 25 25 Max. 3.6 Vcc 115 125 Unit V V

Commercial Junction Operating Temperature Industrial Junction Operating Temperature
C C
5.3 DC Electrical Characteristics
Symbol Parameter IIL Input Leakage Current IOZ Tri-state Leakage Current CIN COUT CBID3 VIL VIH VOH VOL RI Input Capacitance Output Capacitance Bi-direction buffer Capacitance Input Low Voltage Input High Voltage Output High Voltage Output Low Voltage Input Pull-up/down resistance CMOS CMOS 0.7*Vcc IOL=2,4,8,12,16,24mA IOH=2,4,8,12,16,24mA VIL=0V or VIH=VCC 2.4 75 2.7 2.7 Conditions no pull-up or down Min. -1 -1 2.8 4.9 4.9 0.3*Vcc 0.4 Typ. Max. 1 1 Unit uA uA pF pF pF V V V V KOhm
(Under recommended operating conditions and Vcc = 3.0 ~ 3.6V, Tj = 0 to +115 oC)
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MYSON TECHNOLOGY
5.4 Electrical Characteristics
FIGURE 1. MII timing RXCLK0 CRS0/RXDV0 RXD0[3:0] TXCLK0 T7 TXEN0 TXD0[3:0] T8 Valid T5 T6 Valid
MTD502E
Symbol T5 T6 T7 T8
Parameter MII input setup time MII input hold time MII output setup time MII output hold time
Min. 10 10 3 5
Typ.
Max.
Unit nS nS nS nS
Note
FIGURE 2. RMII timing REFCLK CRSDV RXD[1:0] TXEN TXD[1:0] T1 T2 Valid T3 T4 Valid
Symbol T1 T2 T3 T4
Parameter RMII input setup time RMII input hold time RMII output setup time RMII output hold time
Min. 1 1 3 5
Typ.
Max.
Unit nS nS nS nS
Note
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MTD502E Revision 1.3 12/07/2000
MYSON TECHNOLOGY
6.0 128 pin PQFP Package Data
MTD502E
D1 D 102 103 65 64
Symbol A A1 A2 B C D D1
E1
Dimension in inch Min 0.010 Norm Max 0.134 0.117
Dimension in mm Min 0.25 2.73 0.17 0.09 Norm 2.85 0.22 Max 3.40 2.97 0.27 0.20
0.107 0.112
0.007 0.009 0.011 0.004 0.008
0.906 0.913 0.921 23.00 23.20 23.40 0.783 0.787 0.791 19.90 20.00 20.10 0.669 0.677 0.685 17.00 17.20 17.40 0.547 0.551 0.555 13.90 14.00 14.10 0.020 BSC 0.029 0.035 0.041 0.063 BSC 0o 0.004 7o 0o 0.73 0.50 BSC 0.88 1.60 BSC 0.10 7o 1.03
E
E
E1 e L 128 39 L1 y 1 e B 38 z
See Detail B See Detail A Seating Plane
A1
y
Note: 1.Dimension D1 & E1 do not include mold protrusion. But mold mismatch is included. Allowable protrusion is .25mm/.010" per side. 2.Dimension B does not include dambar protrusion. Allowable dambar protrusion .08mm/.003". Total in excess of the B dimemsion at maximum material condition. Dambar cannot be located on the lower radius or the foot. 3.Controlling dimension : Millimeter.
A2
A
B
With Plating Gage Plane L z Base Metal L1 Detail A Detail B
C
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MTD502E Revision 1.3 12/07/2000
MYSON TECHNOLOGY
7.0 80 pin LQFP Package Data
MTD502E
D D1 60 61 41 40
Symbol A A1 A2 b b1 C
E1 E
Dimension in inch Min 0.002 Norm Max 0.063 0.006
Dimension in mm Min 0.05 1.35 0.17 0.17 0.09 0.09 Norm 1.4 0.22 0.20 14.00 BSC 12.00 BSC 14.00 BSC 12.00 BSC 0.50 BSC 0.45 0.60 1.00 REF 0.75 Max 1.60 0.15 1.45 0.27 0.23 0.20 0.16
0.053 0.055 0.057 0.007 0.009 0.011 0.007 0.008 0.009 0.004 0.004 0.008 0.006
C1 D D1
0.551 BSC 0.472 BSC 0.551 BSC 0.472 BSC 0.020 BSC 0.018 0.024 0.030 0.039 REF 0.003 0.003 0.008 0.08 0.08
80 1 e b 20
21
E E1 e L L1 R1 R2
A2 A
-
0.2
See Detail B See Detail A Seating Plane R1 R2
A1
b b1 With Plating
C
Gage Plane L
C1
Base Metal L1 Detail A Detail B
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MTD502E Revision 1.3 12/07/2000

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